1. The Field of the Invention
The present invention relates to processes for forming high aspect ratio submicron VLSI contacts, trenches, and via connections situated on a semiconductor wafer. More specifically, the present invention is a process to provide a high aspect ratio contact, trench, or via with desirable electrical characteristics by depositing a germanium underlayer in a contact, trench, or via opening situated on a semiconductor wafer and followed by an aluminum alloy sputter deposition at low temperature.
2. The Relevant Technology
Recent advances in computer technology and in electronics in general have been brought about at least in part as a result of the progress that has been achieved by the integrated circuit industry in electronic circuit densification and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, attended by an increase in the complexity and number of semiconductor devices aggregated on a single integrated circuit wafer. The smaller and more complex semiconductor devices, including resistors, capacitors, diodes, and transistors, have been achieved, in part, by reducing semiconductor device sizes and spacing and by reducing the junction depth of active regions formed on a silicon substrate of an integrated circuit wafer. The smaller and more complex semiconductor devices have also been achieved by stacking the semiconductor devices at various levels on the wafer.
Among the semiconductor device features which are being reduced in size are the electrical communication interconnect structures through which electrical contact is made between discrete semiconductor devices, or portions of such devices, located on nonadjacent levels of the wafer. These electrical communication interconnect structures include contacts, vias, plugs, trenches, and other structures through which electrical connection is made to discrete semiconductor devices or components of semiconductor devices, located at the varying levels of integrated circuit wafers. These and other such interconnect structures will hereafter be collectively referred to as "interconnect structures." Interconnect structure openings are defined herein as etched conduits between layers which, when filled with conductive material, form the interconnect structure. By way of example, a contact opening is an interconnect structure opening that is filled with a conductive material to form an interconnect structure called a contact. In order to continue in the process of reducing integrated circuit size, new interconnect structure formation methods which overcome certain problems existing in the art are required.
Many of the problems currently encountered when forming interconnect structures arise from the fact that the interconnect structure openings are becoming increasingly smaller. Interconnect structure openings are currently designed with diameters within the half micron range. Also, the aspect ratio of the interconnect structure openings, the ratio of the height of the openings in which interconnect structures are formed to the width of these openings, is becoming very high. Aspect ratios for interconnect structure openings are currently greater than about 3. It is difficult to deposit with good step coverage the necessary conducting filler material in these tiny, narrow, high sided interconnect structure openings. These factors make it difficult to form increasingly miniaturized interconnect structures which retain a high conductivity.
Currently, interconnect structure openings are filled with conducting filler material using one of two processes, chemical vapor deposition (CVD) and physical vapor deposition (PVD), the latter of which is also known as sputtering. Each of these processes has limitations and associated problems. For instance, limitations of the materials that can be deposited with CVD make it impractical for many applications. A shortcoming of existing PVD processes involves the phenomena of cusping, which occurs as a result of nonuniform step coverage, when high aspect ratio interconnect structure openings are being filled.
Cusping occurs during sputtering or reflowing aluminum into interconnect structure openings. Cusping occurs as aluminum aggregates at the top of the interconnect structure opening and overhangs into the center of the interconnect structure opening. Cusping is undesirable, as it blocks the interconnect structure opening before a proper thickness of aluminum can be formed at the bottom of the interconnect structure opening. This results in a partially filled interconnect structure opening with poor electrical connection characteristics and can cause total interconnect structure failure.
Other problems also arise when forming high aspect ratio submicron VLSI interconnect structures. For instance, aluminum is highly desirable as a metallization material because of its conductivity and ease of deposition, but pure aluminum is subject to electromigration failures. Electromigration failures occur when the flow of electrons through the metallization material dislodges aluminum atoms and causes an open circuit condition. This also results in poor electrical conduction or total failure.
As another example of the problems encountered, aluminum must be separated from underlying active regions in order to prevent junction spiking. Junction spiking results in the dissolution of silicon into the aluminum metallization and aluminum into the silicon. Alloy spikes are formed that can extend into the interior of the substrate from the boundary between the electrode and the substrate to cause unwanted short circuit conduction at the junction of the semiconductor in the substrate.
A further problem encountered in forming interconnect structures is the elimination of native silicon dioxide layers that grow in the bottom of the interconnect structure openings. Native silicon dioxide layers are highly insulative and can cause a high contact resistance that can also result in failure of the interconnect structures. Typically, a diffusion barrier of a material such as titanium nitride is used to overcome the problems of spiking and to remove the native silicon dioxide layers. Therefore, methods used for metallizing interconnect structures must be compatible with the currently known methods for depositing diffusion barriers.
One effort to utilize the favorable properties of aluminum germanium alloys to overcome the above and other such problems found in the art is Kikuta K., Kikkawa T., and Aoki M., Al--Ge Reflow Sputtering for Submicron-Contact Hole Filling, IEEE VMIC Conference, Jun. 11, 1991. In the Kikuta paper, an alloy of germanium and aluminum was sputtered from a target into a contact opening having a silicon underlayer. The Kikuta paper recognized that germanium and aluminum have a low eutectic alloying temperature of around 424.degree. C. that allows germanium to readily diff-use into aluminum. Consequently, the Kikuta paper found it desirable to sputter germanium-aluminum alloy as a metallization material, and noted that the alloy flowed more readily into a contact opening and at a lower temperature than does pure aluminum.
In practice, the alloy sputtering method of the Kikuta paper has proven to have certain drawbacks. One problem with sputtering germanium-aluminum alloy into an interconnect structure opening as described in the Kikuta paper is that germanium-aluminum targets are expensive. Also, in order to vary the concentrations of the alloy, a different target is required for each desired concentration. The electromigration resistance of the aluminum and 5% germanium alloy described in the Kikuta paper is no better than that of pure aluminum. Thus, sputtering a germanium-aluminum alloy does not significantly improve electromigration effects, and other materials must also be added to the alloy. This makes the targets even more expensive and makes the process even more inflexible, as a new target is needed for every change in alloy material or concentration.
From the above discussion, it is apparent that a need exists in the art for a method of metallizing an interconnect structure opening having a high aspect ratio that results in high electrical conductivity. The method should utilize the beneficial qualities of germanium-aluminum alloying, such as a low eutectic point and high diffusivity, without the high cost of sputtering a germanium-aluminum alloy and should be capable of use with an additional alloy such as copper that alleviates high electromigration resistance. Such a method would also be highly useful if it could help remove native silicon dioxide from the interconnect structure opening and if it were compatible with diffusion layer processes for overcoming spiking problems.